Complete Verilog HDL programming with Examples and Projects
4.5 /5- Offered byUDEMY
Complete Verilog HDL programming with Examples and Projects at UDEMY Overview
Duration | 8 hours |
Total fee | ₹649 |
Mode of learning | Online |
Credential | Certificate |
Complete Verilog HDL programming with Examples and Projects at UDEMY Highlights
- Earn a certificate of completion from Udemy
- Learn from 1 downloadable resource
- Get full lifetime access of the course material
- Comes with 30 days money back guarantee
Complete Verilog HDL programming with Examples and Projects at UDEMY Course details
- For Undergraduate Electronics and computer science engineering students
- For Graduate students who planning their career in VLSI domain front end (Design & verification)
- For Advanced under graduate students, who willing to do project in front end VLSI design
- Learning Verilog HDL Programming fundamental concepts and properties compare to C Language, feature & advantages of Verilog HDL over VHDL
- VLSI Design flow ( FPGA & ASIC) and Difference between FPGA vs ASIC
- Different design methodologies in Verilog HDL programming with examples
- Behavioral modeling with blocking & Non-Blocking concepts and real time examples
- Test bench Verilog program with examples
- Task & system tasks with examples for random data generator, file based operations and memory load operations, and file representation input & output etc.
- Finite state machine (FSM) with example for both Mealy & Moore and Sequence detector FSM
- Complete design & test bench programming for Memory controllers
- This course discuss the concepts in Verilog HDL programming and properties compared with C-Language and discussing the features and advantages
- In this course we give information related to VLSI design flow for FPGA & ASIC and gives overview about both
- This course gives information on different styles of programming like Gate level, Data flow, Behavioral and switch level with examples
- This course gives clear picture on verification, i.e. simulation and writing a test bench and some general examples like counter, clock diver using counter, pulse generator
- This courses explains how to write verification models using test benches with task and system tasks with Examples
Complete Verilog HDL programming with Examples and Projects at UDEMY Curriculum
Introduction to the course
Preview - course content
Sample program on edaplayground
Introduction to Verilog HDL
Verilog fundamentals
VLSI Design flow (FPGA & ASIC)
VLSI Design flow (FPGA & ASIC)
FPGA vs ASIC
Three levels of verilog design Description
Three levels of verilog design Description
Example: mux_2x1 with 3 abstracts models
Verilog Language constructs, Data types & Compiler Directives
Language constructs -Comments, keywords, identifier, Number specific, Operators
Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory
Compiler Directives
Verilog Program Structure
Verilog Program Structure -Module
Ports
Port Connection Rules
Design Methodologies Approaches
Gate Level Modelling
Gate Level Model Introduction
Example: 4x1 Mux
Example: Full Adder
Tri-state Buffers with Examples
Array of Instance with example
Complete Verilog HDL programming with Examples and Projects at UDEMY Faculty details
Complete Verilog HDL programming with Examples and Projects at UDEMY Entry Requirements
- Prerequisite: basic in C Language
- basics in Digital design
- Not mentioned
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