Learning UVM Testbench with Xilinx Vivado

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Learning UVM Testbench with Xilinx Vivado
at
UDEMY
Overview

Duration	10 hours
Total fee	₹455
Mode of learning	Online
Credential	Certificate

Learning UVM Testbench with Xilinx Vivado
at
UDEMY
Highlights

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Learning UVM Testbench with Xilinx Vivado
at
UDEMY
Course details

Skills you will learn

Investment banking Simulation Software Testing

Who should do this course?

For Anyone interested in learning Design Verification Testbenches with UVM

What are the course deliverables?

Writing testbenches in UVM using Xilinx Vivado Design Suite
Usage of Config db in UVM
Learning TLM in UVM
UVM_Phases and how to effectively use them
UVM classes and their usage

More about this course

The course will discuss the fundamentals of the Verification Methodology
This is a Lab-based course designed such that anyone without prior OOPS or system Verilog experience can immediately start writing UVM components such as Transaction, Generator, Sequencer, Driver, monitor, Scoreboard, Agent, Environment, Test
Numerous coding exercises, projects, and simple examples are used throughout the course to build strong foundations of the UVM

Learning UVM Testbench with Xilinx Vivado
at
UDEMY
Curriculum

Configuring Toolchain for Development

Vivado LIC File

Configuring Toolchain

Code

Common Warning : Simulation object is not Tracable

Common Error : boost::filesystem::remove

Finding Errors in Code

Understanding Reporting Mechanism

Using Reporting Mechanism in Vivado

Code

Important Facts and Terminology

Printing Variable values with Reporting Mechanism

Assignment 1

1 question

Creating Table

Code

Fundamentals of structure

Code

Fundamentals of Class

Code

Important Facts and Terminology

Understanding Extended Class

Code

Important Facts and Terminology

Decoding our Code

Assignment 2

1 question

Important Facts and Terminology

Getting Started with Base Class

Understanding Polymorphism

Understanding Factory Usage part 1

Understanding Factory Usage part 2

Understanding Factory Usage part 3

Sequence_Item

Creating UVM_SEQUENCE_ITEM example 1

Adding Constraints

Creating_UVM_SEQUENCE_ITEM example 2

Understanding reusability

Learning UVM Testbench with Xilinx Vivado
at
UDEMY
Faculty details

Kumar Khandagle

Working as FPGA Developer Lead in India's Finest Financial Technology Firm for the development of a next-generation High-Frequency Trading platform on Xilinx Alveo FPGA Cards