Verilog HDL Fundamentals for Digital Design and Verification
- Offered byUDEMY
Verilog HDL Fundamentals for Digital Design and Verification at UDEMY Overview
Duration | 5 hours |
Total fee | ₹385 |
Mode of learning | Online |
Credential | Certificate |
Verilog HDL Fundamentals for Digital Design and Verification at UDEMY Highlights
- Earn a Certificate of completion from Udemy
- Get a 30 days money back guarantee on the course
- Get full lifetime access of the course material
- Learn from 97 downloadable resources
Verilog HDL Fundamentals for Digital Design and Verification at UDEMY Course details
- For Electronics and Microelectronics hobbyists who want to learn the Verilog Hardware Description Language
- For Beginners who aspire to a career as a Digital Design Engineer or a Functional Verification Engineer
- For Beginners in digital microelectronics and digital circuits design curious about the Verilog Hardware Description language
- For Computer Science, Electronics, Telecommunications, and Microelectronics students who want to learn Verilog for their projects and faculty assignments
- Master the basics of Verilog language for designing synthesizable digital circuits for ASIC / FPGA
- Differentiate between Verilog structural / dataflow / behavioral design styles and how / when to use them in Digital Design and Verification
- Implement combinational and sequential digital circuits using Verilog HDL starting from schematics or functional specifications
- Create and simulate a Verilog testbench for a digital circuit starting from its functional specifications
- Learn the basics of digital circuits theory and we'll focus most of our energy on implementing practical coding examples with real digital circuits using Verilog
- This course with a strong foundation in Verilog HDL for both Digital Design and Functional Verification
- Easily differentiate between different Verilog coding styles (structural, dataflow, behavioral) and how to use them to design synthesizable digital circuits
- At the end of the course you'll master Verilog industry-level coding techniques to get the best results for digital design or verification
- This course is tailored for beginners who are interested in digital microelectronics, digital circuit design and verification
- Learn how to use Verilog for combinational and sequential logic and how to combine the Structural / Dataflow / Behavioral coding styles to obtain digital circuits with a specific functionality
Verilog HDL Fundamentals for Digital Design and Verification at UDEMY Curriculum
Introduction
Welcome
Course Overview
What is Verilog HDL?
Understand Abstraction Levels
Discover the modern digital design flow
Install the Simulator
Discover the Verilog Simulation
Congratulations!
Verilog data types and operators
Action time - sum and product
Hardware Description Language data types
Action time - Multiple procedures
What are Literal Values?
Action time - Literal values
Vectors in Verilog
Action time - Vectors
Verilog Operators - Bit-wise
Action Time - Bit-wise operators
Verilog Operators - Reduction
Action Time - Reduction operators
Verilog Operators - Logical
Action Time - Logical Operators
Action Time - Logical Operators usage
Verilog Operators - Arithmetic
Action Time - Arithmetic Operators
Verilog Operators - Shift
Action Time - Shift Operators
Verilog Operators - Relational
Action Time - Relational Operators
Verilog Operators - Equality
Action Time - Equality Operators
Verilog Operators - Conditional
Action Time - Conditional Operator
Verilog Operators - Concatenation
Action Time - Concatenation Operator
Verilog Operators - Replication
Action Time - Replication Operator
Verilog Operators - Precedence
Action Time - Operators Precedence
Congratulations!
Verilog module
Action time - Do your first testbench
Remember!
What is a Testbench Architecture
Discover Time and Waveforms
Action Time - Generate Waveforms
Verilog design styles
Verilog Structural Design
Action Time - half adder structural
Verilog Dataflow style
Action Time - half_adder dataflow
Verilog_Behavioral_style
Remember!
Action Time - Initial Procedures
Action Time - half_adder behavioral
Design a 1bit full_adder
Action Time - full_adder structural
Action Time - full_adder dataflow
Action Time - full_adder behavioral
Design a 4bit full_adder
Action Time - 4bit_full_adder structural
Action Time - 4bit_full_adder dataflow
Action Time - 4bit_full_adder behavioral
Congratulations!
Verilog Structural Design
What is Structural Design?
Verilog Built-in_Primitives
Action Time - Built-in_gates
Discover the Multiplexer
Action Time - 1bit_mux
Discover the Demultiplexer
Action Time -1bit_demux
The Tri-state buffer
Action Time - tri-state_buffer
How to implement a multiplexer using tri-state buffers
Action Time - mux_tri-state
Discover the 1bit Comparator
Action Time - 1bit_comparator
Remember!
Verilog Combinational Design
What is Combinational logic?
Discover Continuous assignments
Action Time - Continuous assignments
Action Time - Adder Tree
Discover Procedural Assignments
Action Time - Tree Adder Procedural
Discover the Nbit Adder
Action Time - Nbit Adder
Action Time - Nbit Comparator
Differentiate between binary encoders and decoders
Action Time - Nbit Decoder
How to use multiple binary decoders
Action Time - 4to16 binary Decoder
Action Time - 8to3 Encoder
What is a Priority Encoder
Action Time - Priority Encoder1 4to2
Action Time - Priority Encoder2 4to2
Discover bus Multiplexers
Action Time - mux_4x_nbit
Discover bus Demultiplexers
Action Time - demux_4x_nbit
Master the Seven Segment Display Decoder
Action Time - HEX 7segment decoder
How to use digital logic for arithmetic operations
Action time - Design an Arithmetical Logical Unit (ALU)
Remember!
Verilog Sequential Design
Action Time - Clocks Generator
Types of Sequential Digital Logic
Action Time - The D_Latch
Action Time - D_Latch_reset_n
Basics of edge-triggered logic
Action Time - D_Flip_Flop_sync_rstn
Action Time - D_Flip_Flop_async_rstn
Remember!
Discover the Shift Register
Action Time - Shift_Reg_PIPO
Action Time - Shift_Reg_SIPO
Action Time - Shift_Reg_SISO
Action Time - Shift_Reg_PISO
Action Time - Shift_Left_Right_Reg
Discover the Linear Feedback Shift Register
Action Time - Linear Feedback Shift Register
Discover Synchronous Counters
Action Time - Nbit Counter
Action Time - Nbit up/down Counter
Action Time - Modulo_N Counter
Discover Digital Frequency Dividers
Action Time - Clock Divider Nbit
Action Time - Clock Divider by 3
Verilog Functions and tasks
Verilog Functions Basics
Action Time - Verilog Functions1
Action Time - Verilog Functions2
Discover Verilog Recursive Functions
Action Time - Verilog Functions Factorial
Action Time - Verilog Functions Fibonacci
Action Time - Nbit Comparator Function
Verilog Tasks Basics
Action Time - Verilog Tasks Distance Conversion
Action Time - Verilog Tasks Control Shift Reg
Why our code looks like software
Action Time - Shift Reg PIPO buggy
Discover Automated Verification
Action Time - ALU self-checking testbench
Verilog Memory Design
Basics of Semiconductor Memory
Action Time - Single Port Async Read SRAM
Action Time - Single Port Sync Read SRAM
Action Time - Dual Port Async Read SRAM
Action Time - Single Port Sync Read ROM
Verilog HDL Fundamentals for Digital Design and Verification at UDEMY Faculty details
Verilog HDL Fundamentals for Digital Design and Verification at UDEMY Entry Requirements
- Prerequisite: Basic notions of programming languages
- Interest in hardware description languages
- Interest in digital microelectronics, digital circuits design and verification
- Not mentioned
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