Verilog HDL: VLSI Hardware Design Comprehensive Masterclass
5.0 /5- Offered byUDEMY
Verilog HDL: VLSI Hardware Design Comprehensive Masterclass at UDEMY Overview
Duration | 13 hours |
Total fee | ₹490 |
Mode of learning | Online |
Credential | Certificate |
Verilog HDL: VLSI Hardware Design Comprehensive Masterclass at UDEMY Highlights
- Full lifetime access
- Earn a Certificate of completion from Udemy
- Learn from 1 downloadable resource
- Comes with 30 days money back guarantee and full lifetime access
Verilog HDL: VLSI Hardware Design Comprehensive Masterclass at UDEMY Course details
- For A beginner or an intermediate - eager to grasp and understand Hardware Design concepts with HDL
- For Anyone aspiring to build a career in VLSI Circuit Design
- Start designing real life circuits using HDL
- Relationship between hardware and code
- Discussion on every bit of code and hardware
- Application Specific Integrated Circuit
- From basics to key principles for design engineers
- A job oriented exhaustive course on logic design for hardware using the Verilog Hardware Description Language
- Unique, tested and proven structured style and approach followed
- Understand all the intricate details in thinking and understanding hardware design
- After completing the course, you can confidently write synthesizable code for complex hardware design
Verilog HDL: VLSI Hardware Design Comprehensive Masterclass at UDEMY Curriculum
Introduction
Review of VLSI concepts
Quick CMOS basics (added as per request)
What is VLSI?
Review of terms
Minimum feature size
VLSI Design Styles - Full Custom
VLSI Design Styles - Semi Custom
Verilog Basics
Verilog Design Styles
My First Dataflow Style Design
My First Behavioral Style Design
My First Structural Style Design
1-bit Full Adder (Sturctural-1)
1-bit Full Adder (Sturctural-2)
Designing Combinational Logic
4 Valued Logic
Data Types
Number Representation
Bit and Bus
Naming Conventions
Operators - Bitwise
Designing Sequential Logic
Clock, D-Latch and a D-Flip Flop
D-Flip Flop vs D-Latch
D-Latch (Dataflow)
D-Latch (Behavioral)
D-Latch with Asynchronous Reset (Behavioral)
D-Flip Flop (Basic)
Designing Memories
Memory Array Options and Definitions
Single Port Ram - v1
Single Port Ram - v2
Single Port Ram - v3
Single Port Ram - v4
Dual Port Ram - v1
Verilog HDL: VLSI Hardware Design Comprehensive Masterclass at UDEMY Entry Requirements
- Prerequisite: Basics of Digital Logic Design, Fundamentals of VLSI
- Computer architecture
- Not mentioned
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