Altera FPGAs: Learning Through Labs using VHDL
- Offered byUDEMY
Altera FPGAs: Learning Through Labs using VHDL at UDEMY Overview
Altera FPGAs: Learning Through Labs using VHDL
at UDEMY
Grab your Altera FPGA development board and get a hands on approach to learning all about your FPGA through labs
Duration | 2 hours |
Total fee | ₹2,799 |
Mode of learning | Online |
Credential | Certificate |
Altera FPGAs: Learning Through Labs using VHDL at UDEMY Highlights
Altera FPGAs: Learning Through Labs using VHDL
at UDEMY
- Earn a certificate of completion from Udemy
- Learn from 25 downloadable resources & 29 articles
- Get full lifetime access of the course material
- Comes with 30 days money back guarantee
Read more
Altera FPGAs: Learning Through Labs using VHDL at UDEMY Course details
Altera FPGAs: Learning Through Labs using VHDL
at UDEMY
Who should do this course?
- For Engineering Students
- For Engineering Managers
- For Digital Logic Enthusists
- For Individuals pursuing Electrical Engineering
- For Anyone who wants to learn more about VHDL
- For Anyone who wants to take it for fun!
What are the course deliverables?
- Understand the design process for implementing a digital design onto a FPGA
- Program a FPGA
- Replicate all the labs demonstrated in this lab
- How to use the Altera development tools
More about this course
- Altera FPGAs: Learning Through Labs with VHDL teaches students digital design using the hands on approach
- This course focuses on the actual VHDL implementation compared to the theory
- This course is structured such that each section contains a specific topic that is briefly discussed and then you will be given a design to start with to complete the lab
- There is also a demonstration video given as a reference for a working design
Altera FPGAs: Learning Through Labs using VHDL at UDEMY Curriculum
Altera FPGAs: Learning Through Labs using VHDL
at UDEMY
Introduction to the Course
Introduction
Lab 1- BCD Display
BCD Display Explained
BCD Display Lab setup
DE0 Nano SOC Board - BCD Display Demonstration
Lab 2- Linear Feedback Shift Register
Linear Feedback Shift Register Explained
Linear Feedback Shift Register Lab Setup
DE0 Nano SOC Board - LFSR Demonstration
Lab 3- Booth's Algorithm
Booth's Algorithm Explained
Booth's Algorithm Lab Setup
DE0 Nano SOC Board - Booth's Algorithm Demonstration
Lab 4- Barrel Shifter
Barrel Shifter Explained
Barrel Shifter Lab Setup
DE0 Nano SOC Board - Barrel Shifter Demonstration
Lab 5- ALU (Arithmetic Logic Unit)
ALU (Arithmetic Logic Unit) Explained
ALU Lab Setup
DE0 Nano SOC Board - ALU Demonstration
Altera FPGAs: Learning Through Labs using VHDL at UDEMY Faculty details
Altera FPGAs: Learning Through Labs using VHDL
at UDEMY
Jordan Christman
A graduate from the University of Dayton with his Bachelor's degree in Electronic and Computer Engineering Technology. He also graduated from UD with his Master's degree in Electrical Engineering.
Altera FPGAs: Learning Through Labs using VHDL at UDEMY Entry Requirements
Altera FPGAs: Learning Through Labs using VHDL
at UDEMY
Eligibility criteria
- Prerequisite: Basic understanding of binary notation
- Basic understanding of hexadecimal notation
- Basic understanding of logic gates
- Basic understanding of VHDL
Conditional Offer
- Not mentioned
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