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VSD - Physical Design Flow 

  • Offered byUDEMY

VSD - Physical Design Flow
 at 
UDEMY 
Overview

VLSI - Building a chip is like building a city

Duration

5 hours

Total fee

455

Mode of learning

Online

Credential

Certificate

VSD - Physical Design Flow
 at 
UDEMY 
Highlights

  • Earn a Certificate of completion from Udemy
  • Comes with 30 days money back guarantee and full lifetime access
Details Icon

VSD - Physical Design Flow
 at 
UDEMY 
Course details

Skills you will learn
Who should do this course?
  • For Students looking for entry in VLSI World
What are the course deliverables?
  • Industrial Physical Design Flow
  • Develop own Flow as per Specifications
More about this course
  • The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics
  • It is designed for self-learning and will help to polish the Industrial skills in VLSI World
  • This course will cover end-to-end description from basic Device Physics to Chip Design
  • We have contributed anonymously to this website, just to share the part of knowledge learned all these years, with the students keen to learn the basic concepts of the Chip Design

VSD - Physical Design Flow
 at 
UDEMY 
Curriculum

Physical Design Flow Overview

Floor-Planning Steps

Netlist binding and placement optimization

Placement timing and clock tree synthesis

Clock net shielding

Route- DRC Clean - Parastics Extraction- Final STA

Floorplanning

Utilization Factor And Aspect Ratio

Concept Of Pre-Placed Cells

De-coupling Capacitors

Power Planning

Pin Placement And Logical Cell Placement Blockage

Placement

Net-list Binding And Placement

Optimize Placement Using Estimated Wire Length And Capacitance

Optimize Placement Conitnued

Timing Analysis with ideal clock

Setup Timing Analysis And Introduction to Flip-Flop Setup Time

Introduction To Clock Jitter and Uncertainty

Setup Timing Analysis with Multiple Clocks

Multiple Clock Timing Analysis And Introduction To Data Slew Check

Data Slew Check

Clock Tree Synthesis and signal integrity

Clock Tree Routing And Buffering using H-Tree Algorithm

Crosstalk And Clock Net Shielding

Static Timing Analysis With Real Clocks

Hold Timing Analysis Concluded

Multiple Clocks Setup Timing Analysis With Real Clocks

Faculty Icon

VSD - Physical Design Flow
 at 
UDEMY 
Faculty details

Kunal Ghosh
Kunal Ghosh is the Director and co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to launching VSD in 2017, Kunal held several technical leadership positions at Qualcomm's Test-chip business unit. He joined Qualcomm in 2010. He led the Physical design and STA flow development of 28nm, 16nm test-chips.

VSD - Physical Design Flow
 at 
UDEMY 
Entry Requirements

Eligibility criteriaUp Arrow Icon
Conditional OfferUp Arrow Icon
  • Not mentioned

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VSD - Physical Design Flow
 at 
UDEMY 
Students Ratings & Reviews

4.8/5
Verified Icon4 Ratings
R
Rishav Kumar
VSD - Physical Design Flow
Offered by UDEMY
5
Learning Experience: Really great learn static timing analysis, physical design basics
Faculty: Great .. he is from IIT Bombay Really great
Course Support: Good
Reviewed on 19 Nov 2022Read More
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A
Amancha Sanith Kumar
VSD - Physical Design Flow
Offered by UDEMY
5
Learning Experience: Training session was good to learn each flow overview
Faculty: His good to teach every point usage Icc2 shell commands and. Assignment for clock skew find
Course Support: Yes they provide placements
Reviewed on 9 Sep 2022Read More
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VSD - Physical Design Flow
 at 
UDEMY 

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