VSD - Signal Integrity
- Offered byUDEMY
VSD - Signal Integrity at UDEMY Overview
Duration | 7 hours |
Mode of learning | Online |
Credential | Certificate |
VSD - Signal Integrity at UDEMY Highlights
- 7 hours of video content
- Earn a certificate upon successful completion
- Gain Lifetime Access to Courseware
VSD - Signal Integrity at UDEMY Course details
- VLSI Engineers keen to Learn Backend of Chip Design
- Physical Design Engineer
- Students Learning VLSI Engineering
- Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three.Crosstalk is the interference caused due to communication between the circuits.Lets learn to HOW TO REDUCE CROSSTALK ? to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.
VSD - Signal Integrity at UDEMY Curriculum
Introduction
Crosstalk - Why & How Crosstalk occurs in a Chip?
High Routing Density
Dominant Lateral Capacitance
Lower Supply Voltage
Glitch Example and Factors affecting Glitch Height
Basic Crosstalk Glitch Example
Glitch Discharge With High Drive Strength NMOS Transistor
Glitch Discharge With High Drive Strength PMOS Transistor
Factors Affecting Glitch Height - Spacing
Factors Affecting Glitch Height - Aggressor Drive Strength
Factors Affecting Glitch Height - Victim Drive Strength
Factors Affecting Glitch Height - Conclusion
Timming Windows
Single Victim Multiple Aggressors
Introduction to Timing Window
Timing Window Formation
Bucketization based on Timing Windows
Final Glitch Calculation
Crosstalk Delta Delay Analysis
Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction
Impact of Crosstalk Delta Delay on Clock Skew
Setup Timing Analysis Using Real Clocks
Impact of Crosstalk Delta Delay on Setup Timing
Crosstalk Delta Delay - Aggressor Victim Switching in Same Direction
Hold Timing Analysis Using Real Clocks
Impact of Crosstalk Delta Delay on Hold Timing
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