UIUC - VLSI CAD Part I: Logic
4.0 /5- Offered byCoursera
VLSI CAD Part I: Logic at Coursera Overview
Duration | 23 hours |
Start from | Start Now |
Total fee | Free |
Mode of learning | Online |
Difficulty level | Intermediate |
Official Website | Explore Free Course  |
Credential | Certificate |
VLSI CAD Part I: Logic at Coursera Highlights
- 12% started a new career after completing these courses.
- 11% got a tangible career benefit from this course.
- Earn a shareable certificate upon completion.
- Flexible deadlines according to your schedule.
VLSI CAD Part I: Logic at Coursera Course details
- A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc. How do we design these complex chips? Answer: CAD software tools. Learn how to build thesA modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called ?intellectual property? or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this first part of the course is on key Boolean logic representations that make it possible to synthesize, and to verify, the gate-level logic in these designs. This is the first step of the design chain, as we move from logic to layout. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: Computational Boolean algebra, logic verification, and logic synthesis (2-level and multi-level).
- Recommended Background
- Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Exposure to basic VLSI at an undergraduate level is nice -- but it?s not necessary. We will keep the course self-contained, but students with some VLSI will be able to skip some background material.e tools in this class.
VLSI CAD Part I: Logic at Coursera Curriculum
Orientation
Welcome and Introduction
Syllabus
Tools For This Course
Demographics Survey
Computational Boolean Algebra: Basics
Computational Boolean Algebra: Boolean Difference
Computational Boolean Algebra: Quantification Operators
Computational Boolean Algebra: Application to Logic Network Repair
Computational Boolean Algebra: Recursive Tautology
Computational Boolean Algebra: Recursive Tautology?URP Implementation
Week 1 Overview
Week 1 Assignments
Boolean Representation via BDDs and SAT
BDD Basics, Part 1
BDD Basics, Part 2
BDD Sharing
BDD Ordering
Satisfiability (SAT), Part 1
Boolean Constraint Propagation (BCP) for SAT
Using SAT for Logic
Week 2 Overview
Week 2 Assignments
Problem Set #1
2-Level Logic Synthesis, and Multi-Level Logic Synthesis via the Algebraic Model
2-Level Logic: Basics
2-Level Logic: The Reduce-Expand-Irredundant Optimization Loop
2-Level Logic: Details for One Step: Expand
Multilevel Logic and the Boolean Network Model
Multilevel Logic: Algebraic Model for Factoring
Multilevel Logic: Algebraic Division
Multilevel Logic: Role of Kernels and Co-Kernels in Factoring
Multilevel Logic: Finding the Kernels
Week 3 Overview
Week 3 Assignments
Problem Set #2
Multilevel Factor Extract and Don't Cares
Mulitlevel Logic and Divisor Extraction?Single Cube Case
Mulitlevel Logic and Divisor Extraction?Multiple Cube Case
Multilevel Logic and Divisor Extraction?Finding Prime Rectangles & Summary
Multilevel Logic?Implicit Don't Cares, Part 1
Multilevel Logic?Implicit Don't Cares, Part 2
Multilevel Logic?Satisfiability Don't Cares
Multilevel Logic?Controllability Don't Cares
Multilevel Logic?Observability Don't Cares
Week 4 Overview
Week 4 Assignments
Problem Set #3
Auxiliary Quiz of Serious BDDs
Final Exam
Problem Set #4
Final Exam
End of Course Survey
VLSI CAD Part I: Logic at Coursera Admission Process
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