University of Colorado Boulder - Hardware Description Languages for FPGA Design 

Introduction to Hardware Description Languages for FPGA Design

Why Learn VHDL?

FPGA Design Flow

Intro to VHDL: Finite State Machine

How to speak VHDL, first phrases

VHDL Assignments, Operators, Types

VHDL Rules and Syntax, Interface Ports

VHDL in ModelSim: Download and Install

VHDL in ModelSim: Adding to your Toolkit

Submitting VHDL Programming Assignments

Hardware Description Languages for FPGA Design Assessment Strategy

Misson 2-001: Week 1 Readings

Files for Week 1 Programming Assignments

VHDL Find the Code Errors

Module 1 Quiz

Learning to speak VHDL (Intro)

Combinatorial Circuits

Synchronous Logic: Latches and Flip Flops

Synchronous Logic: Counters and Registers

Buses and Tristate Buffers

Modular Designs: Components, Generate and Loops in VHDL

Test Benches in VHDL: Combinatorial

Test Benches in VHDL: Synchronous

Memory in VHDL

Finite State Machines in VHDL

Week 2 Readings

Files for Week 2 Programming Assignments

Module 2 Quiz

Verilog for fun and profit (intro)

Your First Verilog phrase

Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing

Verilog Statements and Operators

Verilog Modules, Port Modes and Data Types

Verilog Structure

Testing with ModelSim

Verilog Evaluation

Submitting Verilog Programming Assignments

Week 3 Readings

Files for Week 3 Programming Assignments

Verilog Find the Errors

Module 3 Quiz

Learning to speak Verilog (intro)

Combinatorial Circuits

Synchronous Logic: Latches and Flip Flops

Synchronous Logic: Counters and Registers

Buses and Tristate Buffers

Modular Design in Verilog

Testbenches in Verilog

Testbenches in Verilog II

Memory with Verilog

Verilog Finite State Machines

Week 4 Readings

Files for Week 4 Programming Assignments

Module 4 Quiz