VLSI Design Flow: RTL to GDS offered by IIIT Delhi
- B++ NAAC accredited
- State University
- Estd. 2008
VLSI Design Flow: RTL to GDS at IIIT Delhi Overview
VLSI Design Flow: RTL to GDS
at IIIT Delhi
Navigating RTL to GDS in 20 Steps - Streamlined Process for Seamless Chip Fabrication and Optimization
Duration | 12 weeks |
Total fee | Free |
Mode of learning | Online |
Official Website | Explore Free Course  |
Credential | Certificate |
VLSI Design Flow: RTL to GDS at IIIT Delhi Highlights
VLSI Design Flow: RTL to GDS
at IIIT Delhi
- Earn a paid certification after completion
- Learn from expert faculty
VLSI Design Flow: RTL to GDS at IIIT Delhi Course details
VLSI Design Flow: RTL to GDS
at IIIT Delhi
Skills you will learn
Who should do this course?
- Semiconductor engineers, digital design and verification engineers, ASIC designers, and VLSI professionals
What are the course deliverables?
- Understand the fundamental principles of VLSI design, from RTL abstraction to GDS implementation
- Master the RTL coding techniques and practices essential for effective VLSI development
- Gain proficiency in simulation and verification methodologies crucial for error-free chip design
- Acquire skills in synthesis and optimization to enhance circuit performance and area efficiency
More about this course
- This course covers the entire RTL to GDS VLSI design flow, going through various stages of logic synthesis, verification, physical design, and testing. Besides covering the fundamentals of various design tasks, this course will develop skills in modern chip design with the help of activities and demonstrations on freely available CAD tools
- This course will enhance the employability of the students and will make them ready to undertake careers in the semiconductor industry
VLSI Design Flow: RTL to GDS at IIIT Delhi Curriculum
VLSI Design Flow: RTL to GDS
at IIIT Delhi
Week 1: Basic Concepts of Integrated Circuit I
Week 2:Overview of VLSI Design Flow III
Week 3:Hardware Modeling
Week 4:Logic Optimization I
Week 5:Formal Verification II
Week 6:Static Timing Analysis I
Week 7:Technology Mapping
Week 8:Design for Test I
Week 9:Basic Concepts for Physical Design I
Week 10:Chip Planning I
VLSI Design Flow: RTL to GDS at IIIT Delhi Faculty details
VLSI Design Flow: RTL to GDS
at IIIT Delhi
Prof. Sneh Saurabh
VLSI Design Flow: RTL to GDS at IIIT Delhi Entry Requirements
VLSI Design Flow: RTL to GDS
at IIIT Delhi
Eligibility criteria
- Basic Course on Digital Circuits (typically taught in the first/second year of UG Program)
Other courses offered by IIIT Delhi
VLSI Design Flow: RTL to GDS
at IIIT Delhi
Student Forum
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VLSI Design Flow: RTL to GDS
at IIIT Delhi
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VLSI Design Flow: RTL to GDS at IIIT Delhi Contact Information
VLSI Design Flow: RTL to GDS
at IIIT Delhi
Address
Okhla Industrial Estate, Phase III, Near Govind Puri Metro Station
Delhi
Phone
01126907404
(For general query)
01126907400
(For admission query)
Email
registrar@iiitd.ac.in
(For general query)
info@iiitd.ac.in
(For admission query)
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