IIT Guwahati researchers make new advancements in memory architectures

IIT Guwahati researchers make new advancements in memory architectures

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New Delhi, Updated on Aug 16, 2021 17:22 IST

Researchers at the institute have developed methods to evenly distribute accesses across the overall memory capacity to reduce the wear-out pressure on heavily written locations. 

IITG

Researchers at the Indian Institute of Technology (IIT), Guwahati, have made fundamental contributions to memory architectures by preventing redundancy in data values and improving slow and frequent writes in the multi-core processor systems. The breakthrough will solve problems in multi-core processor-based systems that need an equally large on-chip memory to commensurate the data demands of the ever-growing applications, preventing energy consumption to ensure the temperature remains under the thermal design power (TDP) budget.  

The research is being led by Prof Hemangee K Kapoor, Department of Computer Science and Engineering (CSE), IIT Guwahati, and comprises a team of research scholars: Sukarn Agarwal, Palash Das, Sheel Sindhu Manohar, Arijit Nath and Khushboo Rani.  

Explaining the challenges of multi-core processor-based systems, Prof Hemangee K Kapoor said, “The application data access patterns are not uniformly distributed and hence leads to several orders of writes to certain memory locations compared to others. Such heavily written locations become prone to wear-out and thus prevents the use of complete memory device without error corrections.” 

To handle this non-uniformity, IIT Guwahati researchers developed methods to evenly distribute the accesses across the overall memory capacity to reduce the wear-out pressure on heavily written locations and also worked in the area which avoids writing redundant values thus prolonging the wear-out. 

He further said, “The team is also working on extending them to off-chip main memory. The future challenges are to handle lifetime enhancement in presence of encryption methods used to secure the non-volatile memory and to handle temperature and process technology driven disturbance errors introduced when the cells are read or written.” 

The researcher’s current and future contributions will help mitigate the drawbacks of promising emerging memories and ease their adaptability. Once some drawbacks are easily removed, scientists can find newer avenues for using such technologies without worrying about its limitations. 

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