IIT Guwahati develops technology to design fast, secure ICs for next-generation computing

The research looks at all aspects of the automated electronics design process like synthesis, verification and security, and contributes towards strengthening the electronics manufacturing ecosystem in our country.

IIT Guwahati develops technology to design fast, secure ICs for next-generation computing

A team of researchers at the Automation, Verification and Security (AVS) Lab at the Indian Institute of Technology (IIT) Guwahati, have worked towards developing secure and dependable integrated circuits (ICs) for faster and efficient computing. The research looks at all aspects of the automated electronics design process like synthesis, verification and security, and contributes towards strengthening the electronics manufacturing ecosystem in our country.

The findings have been published in top-tier journals and conferences of IEEE. The research team is funded by ECR, CRG and Interdisciplinary Cyber-Physical Systems (ICPS) grants from the Department of Science & Technology, Govt. of India and by a Research Fellowship from Intel (India).

The paper has been authored by Chandan Karfa, Associate Professor, Department of Computer Science & Engineering, IIT Guwahati and co-authored by his research students Mohammed Abderehman, Debebdara Senapati, Surajit Das, Priyanka Panigrahi and Nilotpola Sarma. Some alumni who contributed to these endeavors are Ramanuj Chouksey, Jay Oza, Yom Nigam, Abdul Khader and Jayprakash Patidar. The team has collaborated with various international experts. Dr. Chandan Karfa is also the recipient of Qualcomm Faculty Award 2021

With increasing computational demands, there is a need for application-specific processors that can outperform current CPUs. While multicore processors are being used in modern times, their computing power improvements continue to be insufficient.  To cite an analogy for better understanding, running more cars on the road does not necessarily mean you can reach your destination faster; in fact, more cars can lead to congestion and delays. 

Pointing out the importance and need of research in the area of increasing computational power, Dr. Chandan Karfa, said “A promising technology to improve computational efficiency is hardware accelerators. In hardware acceleration, specific tasks can be offloaded to dedicated hardware instead of being performed by the CPU core of the system. For example, visualization processes may be offloaded onto a graphics card, thereby freeing the CPU to perform other tasks.”

IIT Guwahati team emphasize on hardware acceleration specifications that are often written in high-level languages like in C/C++ and are converted to hardware code (or register transfer level or Register−Transfer Level (RTL code), in a process called High-Level Synthesis (HLS).  Due to the complex conversation process, HLS translation may introduce bugs in the design and therefore stringent validation steps are required. The RTL simulators are used to validate HLS, but these are slow and complex.  The team has developed simple and fast tools for HLS validation.

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